Field of the Invention
The invention relates to a NAND flash memory, and particularly relates to a program method of selected pages.
Description of Related Art
In a NAND flash memory, when a page is read or programmed, in order to suppress a noise caused by capacitance coupling between bit lines, one word line separately operates for even-numbered pages and odd-numbered pages. For example, when the even-numbered page is read, the odd-numbered page is grounded, and when the odd-numbered page is read, the even-numbered page is grounded; and when the even-numbered page is programmed, programming of the odd-numbered page is disabled, and when the odd-numbered page is programmed, programming of the even-numbered page is disabled (for example, Japan paten publication No. 11-176177).
Along with propulsion of the low voltage and high integration of the flash memory, besides the capacitance coupling between the bit lines, the influence caused by floating gate (FG) coupling between memory cells also becomes non-ignorable. For example, when data “0” is programmed to the memory cells of the even-numbered page, if the adjacent memory cell is stored with data “1”, a voltage difference between the two memory cells is increased, and a threshold of the adjacent memory cell is increased due to the FG coupling. If the programming is implemented under such environment, a threshold distribution range of the memory cells storing the data “1”, “0” is enlarged, and the reliability of the flash memory is decreased.